Jabil Inc. | Lead Wireless Systems Design Engineer

December 2020 - Present | Warren, NJ

• Design, simulation and documentation of uplink/downlink digital front end, filter designs associated with 5G-NR remote radio units using MATLAB, LTE toolbox, and Xilinx crest factor reduction (CFR) block.

• Developed MATLAB models to solve system level issues associated with LTE radio.

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Florida International University | Graduate Assistant

August 2018 - December 2020 | Miami, FL

Worked on multiple research funded by NSF and used MATLAB/Simulink to model signal processing algorithms.

• Massive-MIMO and mm-wave arrays using FDM for M-fold increase in antennas per ADC/DAC.

Implemented a digital beamforming array receiver of 800 MHz bandwidth per channel at 28 GHz with FDM based approach to reduce ADC consumption. Digital designs were implemented on Xilinx RFSoC ZCU1285 using Xilinx super sample rate (SSR) block-set.

• Sampling using a single ADC for digital antenna arrays by exploiting multi- dimensional signal processing RF circuits.

Proposed a method to reduce ADC requirement by 50% for 2D, single/dual-polarization arrays by exploiting multi-dimensional signal processing RF systems. Transmission line modeling was done using HFSS and AWR.

 

 

Mathworks | Intern at HDL Verifier

September 2019 - December 2019 | Natick, MA

Worked towards the enhancement of ‘HDL Verifier' by MathWorks.

• Used Xilinx Vivado to develop ethernet (PHY interface) IP designs and verified on multiple FPGAs (Artix/Kintex/Virtex).

 

 

University of Akron | Graduate Research Assistant

August ​2016 -  July 2018 | Akron, OH

Worked on multiple research funded by DARPA and NSF on the implementation of advanced digital signal processing systems for MD RF systems.

• Low complexity 1024-point DFT approximator on digital hardware.

A novel approach to approximate DFT for 1024 complex beams with a 75% reduction of the complexity.

• Multiplier-less 64 point DFT approximator on Xilinx FPGA.

A novel approach to approximate DFT for 1024 complex beams with zero multipliers; funded by DARPA.

• Improving ADC figures-of-merit using Sigma-Delta (ΣΔ) noise shaping.

Implementation of ΣΔ architecture in noise-shaping for MD wideband antenna arrays & Focal Plane Array Dish Receivers; funded by NSF.

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SpyGlass by Atrenta (owned by Synopsys Inc) | Intern

January ​2015 -  April 2015

Used SpyGlass, VHDL, System Verilog, ASIC Flow, Xilinx FPGA.

• Developed test cases to verify the changes done to Spyglass software.

• Developed PERL scripts to automate the product verification process.

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