Jabil Inc. | Warren, NJ

Principal Design Engineer (Wireless Systems) September 2023 - August 2024

Lead Design Engineer (Wireless Systems) October 2021 - August 2023

Senior FPGA Engineer (Wireless Systems) December 2020 - October 2021

• Led cross-functional software and firmware teams in developing wireless communication solutions for LTE and 5G NR O-RAN Remote Radio Units (RRUs), significantly enhancing product performance and reliability. 

• Defined 5G NR implementation requirements for projects and guided the digital hardware design team to meet 3GPP specifications with optimized complexity; produced comprehensive architectural and implementation guidance documents.

• Performed filter design, Crest Factor Reduction (CFR) simulation, cancellation pulse generation, and end-to-end system modeling and simulation for uplink, downlink, PRACH Digital Front End (DFE), and LPHY firmware in single, dual, and tri-band LTE / 5G NR (FDD / TDD) radios. 

• Generated stimulus test vectors for RTL simulation, integrated Xilinx C-models for hard IPs, and developed executable models for UVM test benches. 

• Developed scripts to extract control-plane and user-plane O-RAN data from PCAP files containing Ethernet packets for bit-accurate system modeling. 

• Contributed to strategic decision-making for massive MIMO implementation on O-RUs and determined O-RAN functional splits to optimize resource allocation and project timelines. 

• Conducted in-depth studies on mixed OFDM / OTFS implementations and Passive Intermodulation (PIM) cancellation techniques, leading to improved system efficiency.

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Florida International University | Graduate Assistant

August 2018 - December 2020 | Miami, FL

Worked on multiple research funded by NSF and used MATLAB/Simulink to model signal processing algorithms.

• Massive-MIMO and mm-wave arrays using FDM for M-fold increase in antennas per ADC/DAC.

Implemented a digital beamforming array receiver of 800 MHz bandwidth per channel at 28 GHz with an FDM-based approach to reduce ADC consumption. Digital designs were implemented on Xilinx RFSoC ZCU1285 using Xilinx super sample rate (SSR) block-set.

• Sampling using a single ADC for digital antenna arrays by exploiting multi- dimensional signal processing RF circuits.

Proposed a method to reduce ADC requirement by 50% for 2D, single/dual-polarization arrays by exploiting multi-dimensional signal processing RF systems. Transmission line modeling was done using HFSS and AWR.

 

 

Mathworks | Intern at HDL Verifier

September 2019 - December 2019 | Natick, MA

Worked towards the enhancement of ‘HDL Verifier' by MathWorks.

• Used Xilinx Vivado to develop ethernet (PHY interface) IP designs and verified on multiple FPGAs (Artix/Kintex/Virtex).

 

 

University of Akron | Graduate Research Assistant

August ​2016 -  July 2018 | Akron, OH

Worked on multiple research funded by DARPA and NSF on the implementation of advanced digital signal processing systems for MD RF systems.

• Low complexity 1024-point DFT approximator on digital hardware.

A novel approach to approximate DFT for 1024 complex beams with a 75% reduction of the complexity.

• Multiplier-less 64-point DFT approximator on Xilinx FPGA.

A novel approach to approximate DFT for 1024 complex beams with zero multipliers funded by DARPA.

• Improving ADC figures-of-merit using Sigma-Delta (ΣΔ) noise shaping.

Implementation of ΣΔ architecture in noise-shaping for MD wideband antenna arrays & Focal Plane Array Dish Receivers; funded by NSF.

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SpyGlass by Atrenta (owned by Synopsys Inc) | Intern

January ​2015 -  April 2015

Used SpyGlass, VHDL, System Verilog, ASIC Flow, Xilinx FPGA.

• Developed test cases to verify the changes done to Spyglass software.

• Developed PERL scripts to automate the product verification process.

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