Where the work happened

• Signal Processing Engineer2025-Present

System and verification modeling for multiband LTE and 5G NR O-RAN radio units. I own the versioned golden models, downlink, uplink, low-PHY, and PRACH, that generate bit-exact RTL and fronthaul test vectors against the vendor fixed-point IP C-models for firmware sign-off, across 17 bands and carriers from 3 to 100 MHz. Since February 2025 I have taken 27 production debug investigations down to root cause, across TDD and FDD bring-up, PRACH, observation-receiver, and gain issues, on lab and field captures from OEM and partner test stacks.

• Bit-accurate uplink MRC combining for O-RAN shared-cell DAS, up to 4 RUs x 8 antennas: matched the floating-point reference within 0.01 dB SINR and held 34 dB SINR where equal-gain combining collapsed below 8 dB.
• An 18-channel polyphase filter bank for a spectrum-sensing O-RU, 691.2 Msps in, 18 x 38.4 Msps out, feeding a signal classifier on NVIDIA Orin; two independently built implementations proven bit-identical.
• The 846-check PRACH harness, the lab waveform analyzer, and the fronthaul power tool live under Systems.
• System modeling and standards-grounded gap analysis for Airspan 6G research.

• Principal Design Engineer, Wireless Systems2023-2024
• Lead Design Engineer, Wireless Systems2021-2023
• Senior FPGA Engineer, Wireless Systems2020-2021

Four years of O-RAN radios, single band to tri band, promoted twice along the way. I ran software and firmware workstreams, defined NR implementation requirements, and wrote the architecture and implementation documents the digital design team built to. In 2022 that included CFR cancellation-pulse analysis delivered to a major OpenRAN program partner. I also spent a fair amount of time in front of customers explaining passive intermodulation, which taught me more about what a radio has to be than any specification did.

• Graduate Research Assistant, PhD2018-2020

PhD research on hardware-efficient massive MIMO. I built a 28 GHz digital beamforming array receiver that used one ADC per four antennas instead of one per antenna, and a multidimensional scheme that halved the ADC count for 2D arrays. The lab had a few RFSoC boards and quite a lot of patience.

• Engineering Intern2019

A summer on HDL Verifier workflows and Ethernet PHY IP across a few FPGA families. Two awards in the intern hackathon.

• Graduate Research Assistant2016-2018

DARPA, NSF, and AFRL funded research on multidimensional DSP for RF systems. This is where I first fell for approximate DFTs and multidimensional sigma-delta ADCs, and where I learned that a good algorithm and a bad one can look identical on paper and very different on silicon.

• Product Verification Intern2015

First exposure to ASIC verification: Spyglass, SystemVerilog, VHDL, and a great deal of Perl.