Where the work happened

• Signal Processing EngineerJan 2025 to present

O-RAN 7.2x radio units: bit-accurate DFE and low-PHY reference modeling, FPGA IP verification, and the fronthaul test tooling the lab teams run. I own the golden models of the downlink, uplink, low-PHY, and PRACH chains, versioned and used to generate the RTL and fronthaul test vectors firmware is signed off against, and I generate the 3GPP test waveforms the system test, RF test, firmware verification, and software teams work from.

• I built and maintain the bit-accurate downlink and uplink DFE and low-PHY reference models that generate the RTL golden vectors, so RTL is compared bit for bit rather than to a tolerance: NR and LTE test models through IFFT and FFT, CFR, the vendor's channel-filter and mixer IP C-models, and O-RAN BFP at 8, 9, 10, 12, and 14 bits, across 3 to 100 MHz including combined-band carriers such as B28 with B20.
• I built the bit-accurate PRACH receive-chain model, from the vendor's PRACH DDC and decimation through CP removal, FFT, subcarrier extraction, BFP and U-plane packing, and detection, covering every LTE format and all NR FR1 formats, long and short preambles, FDD and TDD.
• The O-RAN fronthaul power and PAPR tool and the uplink EVM and PRACH analyzer, including its RU to DU full-scale alignment check, live under Systems.
• I built the expected versus captured IQ comparison GUI used in bring-up: cross-correlation delay alignment, overlaid PSD and PSD difference, and dBFS power readout for hex, BFP, .mat, and raw binary captures.
• I re-clocked CFR from 491.52 to 245.76 MSPS and redesigned the cancellation pulses and channel filters for 3 to 20 MHz to meet an operator's 3 MHz carrier requirement (a 3 MHz channel filter is not realizable at 30.72 MSPS), tuning cutoff and pulse length against a per-symbol constellation EVM metric rather than the vendor's RMS figure: 2.17 to 2.23% EVM at 3, 5, and 10 MHz inside ACLR and OBUE margin.
• I built a multiband PIM planner that catalogs IM3, IM5, and IM7 products for multi-carrier downlink and flags uplink-band hits, checked by hand against a B71, B29, and B14 stack.

• Principal Wireless Systems Design EngineerDec 2023 to Aug 2024
• Lead Wireless Systems Design EngineerSep 2021 to Dec 2023
• Senior FPGA Design EngineerDec 2020 to Sep 2021

Four years of O-RAN radios, single band to tri band. I ran software and firmware workstreams, defined NR implementation requirements, and wrote the architecture and implementation documents the digital design team built to. I also spent a fair amount of time in front of customers explaining passive intermodulation, which taught me more about what a radio has to be than any specification did.

• Led the software and firmware workstreams for LTE and 5G NR O-RAN radio units from single-band to tri-band through commercial release: defined NR implementation requirements, wrote the architecture and implementation documents the digital design team built to, weighed massive MIMO and O-RAN functional-split options against implementation complexity, resources, and timelines, and briefed customers on passive intermodulation.
• Primary author of the DFE System Design Documents for two radio lines, a B3 FDD radio (5 to 40 MHz) and a 100 MHz TDD radio: the interpolation chain to 983.04 MSPS, pulse-shaping filters derived from TS 38.104 guard-band rules and grouped into five classes covering thirteen bandwidths, CFR cancellation-pulse configuration, and uplink decimation and PRACH routing.
• Authored the firmware implementation guides for the NR symbol phase-compensation term of TS 38.211 section 5.4 (quadrant-folded trigonometric LUT, 4097-entry table, 21-bit minimum phase accumulator, numerology-dependent parameters, since a wrong term shows up as a rotated constellation) and for RFSoC pre-emphasis (per-subcarrier 16-bit LUTs flattening pulse-shaping passband droop for 5 to 30 MHz, with the LTE and LTE plus NB-IoT edge cases per TS 38.104 section 5.7.3).
• Wrote the uplink DFE receiver test plan for LTE, NR, and MSR against TS 36.141 and TS 38.141: reference sensitivity, dynamic range, in-channel and adjacent-channel selectivity, and narrowband, in-band, and out-of-band blocking, with bottom, mid, and top frequency coverage per band and VRB-offset sweeps.
• Designed 8-block PRACH detection within the PRACH core's 4K-FFT limit by cascading two 4K FFTs as a filter bank with per-block phase-rotation correction, and mapped LTE and NR PRACH subcarriers onto the core's FFT sizes and decimation ratios.
• Ran filter design, CFR simulation, and cancellation-pulse generation for uplink, downlink, and PRACH DFE firmware: a hard-clipper threshold sweep in 0.1 dB steps that set the 7.8 dB PAR operating point for E-TM 3.1, a first- and second-difference slew-rate detector for post-IFFT overflow, and cancellation-pulse analysis delivered to a major OpenRAN program partner in 2022.
• Generated RTL stimulus vectors, integrated the vendor's hard-IP C-models, developed executable models for UVM testbenches, and wrote PCAP tooling to extract O-RAN C-plane and U-plane data for bit-accurate system modeling.

• Graduate Research Assistant, PhD2018-2020

PhD research on hardware-efficient massive MIMO. I built a 28 GHz digital beamforming array receiver that used one ADC per four antennas instead of one per antenna, and a multidimensional scheme that halved the ADC count for 2D arrays. The lab had a few RFSoC boards and quite a lot of patience.

• Engineering Intern2019

A summer on HDL Verifier workflows and Ethernet PHY IP across a few FPGA families. Two awards in the intern hackathon.

• Graduate Research Assistant2016-2018

DARPA, NSF, and AFRL funded research on multidimensional DSP for RF systems. This is where I first fell for approximate DFTs and multidimensional sigma-delta ADCs, and where I learned that a good algorithm and a bad one can look identical on paper and very different on silicon.

• Product Verification Intern2015

First exposure to ASIC verification: Spyglass, SystemVerilog, VHDL, and a great deal of Perl.